1. Field of the Invention
The present invention relates to a multiple power supply semiconductor device and a signal level converting method in the device, and particularly to a multiple power supply semiconductor device and a signal level converting method that can implement low power consumption with small hardware volume.
2. Description of Related Art
FIG. 3 is a block diagram showing a configuration of a multiple power supply semiconductor device to which a conventional signal level converting method is applied. In this figure, the reference numeral 1 designates an SDRAM core; 2 designates its power supply; 3 designates a supply voltage converter; 4 designates a logic circuit; 5 designates an SDRAM test circuit; 6 designates a level shifter; 7 designates an input-output circuit; and 8 designates an input-output level converter.
The individual semiconductor circuits in the multiple power supply semiconductor device consist of transistors with different withstanding voltages due to differences in gate oxide thickness. In the present example as shown in FIG. 3, since the SDRAM core 1 is provided not only with a 3.0 V supply voltage, but also with a 2.5 V supply voltage output from the supply voltage converter 3, it employs two types of transistors: first transistors with a gate oxide thickness Tox of 57 .ANG. and a withstanding voltage of 2.7 V; and second transistors with a gate oxide thickness Tox of 75 .ANG. and a withstanding voltage of 4.0 V. On the other hand, since the logic circuit 4, SDRAM test circuit 5 and level shifter 6 are provided only with a 1.3 V supply voltage, or with the 1.3 V supply voltage and the 2.5 V supply voltage output from the supply voltage converter 3, they employ only the first transistors with the gate oxide thickness Tox of 57 .ANG. and the withstanding voltage of 2.7 V.
Next, the operation of the conventional device will be described.
In a normal read operation mode, an input signal from the outside is transferred from the input-output circuit 7 to the input-output level converter 8 which converts the signal level from 3.0 V to 1.3 V. The logic circuit 4, which is fed with the 1.3 V supply voltage, receives the signal whose level is converted to 1.3 V, processes it and provides the processing result to the level shifter 6. Accordingly, the signal level of the signal transferred from the logic circuit 4 to the level shifter 6 is 1.3 V. The level shifter 6, which is provided with the 1.3 V supply voltage and the 2.5 V supply voltage the supply voltage converter 3 produces by converting the 3.0 V supply voltage, converts the level of the signal fed from the level shifter 6 from 1.3 V to 2.5 V, and transfers it to the SDRAM core 1.
The SDRAM core 1 starts its access operation in response to the signal with the 2.5 V signal level transferred from the level shifter 6, and reads data from a designated address. The signal level of the read-out data is 2.5 V. The signal of the read-out data is transferred to the level shifter 6 which converts its level from 2.5 V to 1.3 V, and supplies it to the logic circuit 4. The logic circuit 4 processes the signal of the 1.3 V signal level, and transfers the resultant signal to the input-output level converter 8. The signal transferred from the logic circuit 4 to the input-output level converter 8 has a signal level of 1.3 V. The input-output level converter 8 converts the level of the transferred signal from 1.3 V to 3.0 V, and supplies it to the input-output circuit 7 to be output.
Although the foregoing is the description of the read operation by the SDRAM core 1 in response to the external signal in the normal mode, a write operation to the SDRAM core 1 is carried out in the same manner in response to an external signal.
In an SDRAM test mode, a test of the SDRAM core 1 is carried out in a similar manner as the operation in the normal mode. Specifically, a test signal converted to 1.3 V by the input-output level converter 8 is processed by the SDRAM test circuit 5 in the logic circuit 4, and is transferred to the level shifter 6. The level shifter 6 converts the level of the test signal from 1.3 V to 2.5 V, and transfers it to the SDRAM core 1. Reversely, a response to the test signal is transferred from the SDRAM core 1 to the level shifter 6 which converts its signal level from 2.5 V to 1.3 V. The SDRAM test circuit 5 processes the response signal with the 1.3 V level, and the input-output level converter 8 converts the signal level to 3.0 V to be output. Thus, the integrity of the SDRAM core 1 is verified.
In FIG. 3, the signal flow involved in the normal read/write mode is denoted by thin lines, whereas the signal flow involved in the SDRAM test mode is denoted by thick lines.
Such a conventional signal level converting method is disclosed in Japanese patent application laid-open Nos. 59-139725/1984 and 9-148913/1997, for example.
The conventional signal level converting method thus carried out has the following problems. First, since the level shifter 6 converts the levels of all the signals transferred between the SDRAM core 1 and the logic circuit 4 including the SDRAM test circuit 5, it is unavoidable that the hardware volume grows large. Second, since the supply voltage converter 3 must provide the 2.5 V supply voltage to the level shifter 6 besides the SDRAM core 1, it is necessary to take account of the power consumption of the logic section as well as that of the SDRAM core 1, which requires a large current capacity, resulting in an increase in the hardware volume and power consumption.